1. Field of the Invention
The present invention is related to charge-reading circuits designed especially for the reading of charges picked up by solid-state image sensors.
2. Description of the Prior Art
These charge reading circuits are of the charge integrator type. Prior art read circuits 30 of this kind are shown in FIG. 1. More particularly, FIG. 1 shows an image sensor 1 with a plurality of photosensitive dots P1 to P9 each connected between a row conductor Y1 to Y3 and a column conductor X1 to X3. Each photosensitive dot P1 to P2 is formed by a photosensitive diode Dp series-connected with a switch function element in the form of a selection-switching diode Dc. A transistor could have been used as a switch function element. The row conductors Y1 to Y3 are connected to at least one addressing device 3 while the column conductors X1 to X3 are connected to a read device CL comprising as many read circuits 30 as there are column conductors X1 to X3. These read circuits 30 are capable, during an integrating operation, of converting charges into voltage. These charges are collected at the junction point A between the photosensitive diode Dp and the switch function element Dc of a photosensitive dot to which they are connected. This collecting of charges takes place when the photosensitive diodes Dp are in a receptive state and. the photosensitive dots are exposed to a piece of information to be sensed.
The reading of all the photosensitive dots connected to one and the same row conductor Y1 to Y3 is done at the same time, row conductor by row conductor. The photosensitive dots of one and the same column conductor X1 to X3 are read, each in turn, by the read circuit 30 connected to this column conductor.
It is sought to ensure that the conversion is done with a relationship of proportionality that is as constant as possible between the quantity of charges collected and the voltage delivered by the read circuit 30 so that the image delivered by the read device CL is as close as possible to the image to be detected.
Each read circuit 30 has an input E formed by one of the electrodes of the pair formed by the drain d and the source s of a read MOS transistor M1. This input E is connected to one of the column conductors X1 to X3 on which the collected charges flow. The output S of the read circuit 30 is obtained on the side that has the other electrode (source s or drain d) of the read MOS transistor M1 which is connected to one of the plates of an integration capacitor C. The other plate receives a reference voltage VDR. There is a direct transfer of the charges injected into the input E of the read circuit 30 through the read MOS transistor M1 and integration by the capacitor C if the transistor is conductive. The transfer of the charges can be accelerated by the application of a control voltage V1 at the gate g of the read MOS transistor M1. This control voltage V1 is delivered by an acceleration inverter amplifier A1 whose input is connected to the input E of the read circuit 30. The voltage V1 is such that:
V1=xe2x88x92Gxc3x97Ve
with Ve as the input voltage E of the read circuit 30 and G as the voltage gain of the amplifier A1. In practice, the gain G is high and is chosen for example to be between 500 and 1000 so as to reduce the noise associated with the transfer of the charges between the input E and the output S. The amplifier inverter A1 is supplied with a negative supply voltage VR (for example in the range of xe2x88x922.75 volts).
It is furthermore planned, in parallel with the capacitor C, to obtain a switch I in order to reinitialize it when all the charges coming from a photosensitive dot have been integrated and before integrating those coming from another photosensitive dot.
This type of read circuit 30 is a one-way circuit and this is a drawback because it can integrate only charges with a single type of polarity, namely either positive charges (holes) or negative charges (electrons). The type of polarity is conditioned by the nature of the channel of the read MOS transistor M1.
If the MOS transistor M1 is an N channel transistor, the charges injected into the MOS transistor M1 can be none other than electrons and the voltage VDR is more positive than the voltage Ve. If, instead of electrons, it is holes that are injected, the input voltage Ve becomes more positive then the reference voltage VDR and the control voltage V1 then blocks or turns off the read MOS transistor M1. So long as the read MOS transistor M1 is off, the charges injected into the input E of the read circuit 30 cannot be integrated and the pieces of information that they convey are then lost. The timing diagrams of FIGS. 2a to 2e respectively show the forms of the quantity of charges reaching the input E of one of the read circuits 30, the voltage Ve at the input E of the circuit, the control voltage V1 applied to the gate g of the read MOS transistor M1, the voltage Vs at output S of the read circuit 30 and finally the state of the switch I which reinitializes the capacitor C. It is assumed that, in the example described, the MOS transistor M1 is an N channel transistor and that the read circuit can read quantities of negative charges or electrons. If the transistor were a P channel transistor, it would be capable of reading holes, and the signs of the voltages and their direction of variation would be reversed in the following description.
When electron packets reach the input E of the read circuit, the voltage Ve at the input E of the circuit 30 decreases suddenly from a basic value Vb, the control voltage V1 for its part starts rising from an initial value V1i up to a value V1d and the MOS transistor M1 gets unblocked. The basic value Vb is equal to the sum of the supply voltage VR of the acceleration amplifier A1 and the threshold voltage of the transistor included in the amplifier. The amplifier A1 is not described in detail.
The charges can be integrated. The voltage Vs at the output S, initially taken to the value VDR, starts decreasing until it reaches the value Vs1 after the integration of all the charges received. When all the charges are integrated, the voltage Ve at its input returns to its base value Vb, the voltage V1 at the output also returns to the initial value V1i and the read MOS transistor M1 goes off. The voltage Vs keeps the value Vs1 reached so long as the resetting switch I remains open and then returns to the reference value VDR as soon as it is closed.
When a photosensitive dot is defective, i.e. when at least one of its components (photosensitive diode Dp or switch function element Dc) is out of operation, a large number of holes reaches the input E of the read circuit 30 to which it is connected. This number is generally far greater than the number of the electrons reaching a photosensitive dot in functioning condition even if it has been exposed TO A highly intense light flux. This arrival of holes is called reverse over-dazzling. The voltage Ve at input greatly increases. The control voltage V1 which follows the variations in the voltage Ve at the input, in reversing and amplifying these variations, decreases sharply. The MOS transistor M1 which was off or blocked remains blocked. The voltage Vs at the output S does not vary but remains at the reference value VDR. The closing of the resetting switch I has no effect on the voltage Vs at the output. When electrons reach the input E of the read circuit once again, the voltage Ve at the input decreases slightly and the control voltage V1 decreases too, but this is not enough to unblock the read MOS transistor M1. The voltage Vs at the output does not vary and the information carried by the electrons that reach the input E is lost. At the input of the read circuit, at least as many electrons as holes must be recovered in order to unblock the read MOS transistor M1. In the image detected, this takes the form of a column portion that remains black. This portion corresponds to all the photosensitive dots of the column read after the one that is defective so long as the MOS transistor M1 has not been unblocked. It is not rare for the black column portion to correspond to more than about ten photosensitive dots. This defect cannot be tolerated.
Similarly, if the read MOS transistor M1 is a P channel type transistor, the charges injected through the MOS transistor M1 can only be holes and the reference value VDR is more negative than the voltage Ve at input. If, instead of holes being injected, it is electrons that are injected, the voltage Ve at the input becomes more negative than the reference value VDR, and the control voltage V1 then blocks the MOS transistor M1. So long as the MOS transistor M1 is blocked, no more charges can be integrated and the information that they carry is then lost.
In any case, this type of read circuit 30 goes off when it has to work with-charges having polarity opposite to the polarity for which it was designed.
The present invention seeks to eliminate the blocking of the charge-reading circuit during the reading of the charges coming from a defective photosensitive dot and makes the circuit operational for the reading of the first non-defective photosensitive dot that follows. A defective photosensitive dot does not disturb the subsequent reading, by the same circuit, of other photosensitive dots which for their part are in a functional state.
To achieve this goal, the present invention proposes a circuit for the reading of charges injected at its input, comprising a read MOS transistor and an integration capacitor mounted between a first electrode of the drain-source pair of the read MOS transistor and a reference potential. The type of MOS transistor conditions the polarity of the charges that the read circuit is capable of reading without getting blocked. The input of the circuit is at the second electrode of the drain-source pair of the read MOS transistor. The charges injected at the input must cross the read MOS transistor to be integrated by the capacitor. The read MOS transistor is controlled by a a control voltage that varies in a manner that is substantially inversely proportional to the input voltage. The circuit has means to detect the arrival, at the input, of charges with a polarity opposite to the polarity of the charges that it is capable of reading and means for the imposing, on the input voltage, after a detection of this kind, of an equilibrium value equal or close to a basic value that it takes between two successive operations of integrating charges with the desired polarity so as to prevent a prolonged blocking of the read MOS transistor at the arrival of charges with a desired polarity.
The means for detecting the arrival of charges of an undesired polarity may be obtained by an inverter amplifier whose input receives the control voltage. The amplifier has a selection-switching threshold. The crossing of this threshold by the control voltage, in moving away from the initial value taken when the value of the voltage at.input is the basic value, expresses the presence of charges with an undesired polarity at input.
The means used to impose the equilibrium value may comprise an unblocking MOS transistor. One of the electrodes of the drain-source pair of this MOS transistor is connected to the input while the other electrode of the drain-source pair is taken to the equilibrium value. This MOS transistor is controlled by the output of the means to detect the arrival of charges with an undesired polarity.
To prevent the appearance of unwanted oscillations, the read circuit may comprise means to delay the imposing of the equilibrium value with respect to the detection of the arrival of the charges with undesired polarity.
The means used to delay the imposing of the equilibrium value may be obtained by a delay switch which, so long as it is open, prevents the application of the equilibrium voltage at input. This delay switch is connected to one of the electrodes of the drain-source pair of the unblocking MOS transistor.
With a view to simplification and efficiency, the control of the delay switch may be made synchronous with that of the reinitializing switch parallel-connected with the integration capacitor.
The selection-switching threshold is lower than the initial value of the control voltage when the read circuit is designed to read electrons and higher than this voltage when the read circuit is designed to read holes.
Similarly, the equilibrium value is lower than or equal to the basic value when the read circuit is designed to read electrons and it is higher than or equal to this basic value when the read circuit is designed to read holes.
The control voltage can be delivered by an inverter amplifier mounted between the input and the gate of the read MOS transistor. It is preferable to choose this high gain amplifier.